Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, a software portion of the design is compiled into software that is executable by a hard processor disposed on a single semiconductor chip with resources of an programmable logic device (PLD). A first synthesized version of a hardware portion of the design is generated for the PLD. A synthesized memory scrubber having an empty block for an address counter is generated, as well as a triple modular redundant (TMR) address counter. The memory in the first synthesized version of the hardware portion of the design is replaced with the memory scrubber, and a complete set of netlists is generated, including a TMR hardware portion of the design and a single instance of the synthesized memory scrubber. A configuration bitstream is generated from the complete set of netlists and stored for later use.


< Yield analysis and improvement using electrical sensitivity extraction

> Method, system, and article of manufacture for reducing via failures in an integrated circuit design

> Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device

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