A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit.

 
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> Implementing a user design in a programmable logic device with single event upset mitigation

> Method, system, and article of manufacture for reducing via failures in an integrated circuit design

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