A method for applying test vectors to a device under test (DUT) at a speed of
the
DUT is disclosed. A pattern memory is re-organized into m modules, where m is a
DUT/pattern memory speed ratio. Delay circuits in address lines of each module
are programmed such that an address signal for a qth module is delayed by (q-;1)
delay units, where each delay unit is equivalent to one DUT clock cycle. Patterns
for each test are stored in these modules according to [n mod m]; where n is a
number of patterns in a test. Identical addresses are simultaneously applied to
the delay circuits of the m modules according to a fixed address sequence at a
rate f equal to or slower than the operating frequency of the pattern memory, such
that a period of f is equal to or greater than (m-;1) delay units.
