A method is provided for processing a semiconductor topography. In particular,
a method is provided for decreasing the threshold voltage magnitude of a first
transistor being formed within the substrate while simultaneously increasing the
threshold voltage magnitude of a second transistor being formed within the substrate.
In some embodiments, a width of the first transistor may be larger than a width
of the second transistor. In addition or alternatively, the method may include
performing a first implantation corresponding to a threshold voltage magnitude
above a desired value for the first transistor. The method may further include
performing a second implantation to simultaneously lower the threshold voltage
magnitude of the first transistor and raise a threshold voltage magnitude of the
second transistor. In some embodiments, the method may include introducing dopants
of a first conductivity type into a first transistor channel dopant region and
a second transistor channel dopant region simultaneously.
