FeRAM having test circuit and method for testing the same

   
   

A nonvolatile ferroelectric memory device comprising a cell array having a multi-bitline structure comprises a plurality of cell array blocks, common data buses shared by the plurality of cell array blocks to transmit data stored in the cell array blocks, a sense amplifier array which compares a sensing voltage of the data transmitted through the common data buses with a reference voltage, a reference voltage controller which adjusts the reference voltage in response to test mode control signal externally applied thereto, and a column selecting controller which selects the predetermined number of cell array blocks in response to the test mode control signals and outputs sensing voltages of the selected cell array blocks to the common data buses at the same time. Accordingly, the nonvolatile ferroelectric memory device can selectively test more than two cell array blocks as well as a single cell array block having a 1T1C structure simultaneously by using just control signals without additionally modifying an internal circuit.

 
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