In response to a clock cycle and a pending READ command for data with a variably
recurring access latency, a clock cycle count is adjusted. If a latency value has
not been locked and if the READ command is a first READ command, the clock cycle
count is stored as a locked latency value upon receiving a synchronized data available
event (DQS for instance). Each subsequent READ command has an associated clock
cycle count to enable pipelining wherein the clock cycle count for each READ starts
incrementing when the individual READ command is issued. For subsequent READ commands,
if the cycle count compares favorably with the locked latency value, data can be
sampled safely from the interface at the identical latency for every READ request
issued. The locked latency value can be read and/or written by software/hardware
such that the read latency is consistent across multiple devices for reproducibility
during debug.
