Clock driver circuit having upper and lower transistors.sub.1 and upper and lower transistors.sub.2. Voltage node.sub.1 coupled to electrodes of upper transistor.sub.1 and upper transistor.sub.2. Voltage node.sub.2 coupled to electrodes of lower transistor.sub.1 and lower transistor.sub.2. Coupling transistor.sub.1 couples another electrode of upper transistor.sub.1 to another electrode of lower transistor.sub.2. Coupling transistor.sub.2 couples another electrode of upper transistor.sub.2 to another electrode of lower transistor.sub.1. Two series.sub.1 capacitors couple the another electrode of upper transistor.sub.1 to the another electrode of lower transistor.sub.1. Two series.sub.2 capacitors couple the another electrode of upper transistor.sub.2 to the another electrode of lower transistor.sub.2. Node intermediate the two series.sub.2 capacitors provides in-phase clock output. Node intermediate the two series.sub.1 capacitors provides anti-phase clock output. In-phase clock input is coupled to control inputs of upper transistor.sub.1, coupling transistor.sub.1 and lower transistor.sub.1. Anti-phase clock input is coupled to control inputs of upper transistor.sub.2, coupling transistor.sub.2 and lower transistor.sub.2.