A conditional instruction architected to receive one or more operands as
inputs, to output to a target the result of an operation performed on the
operands if a condition is satisfied, and to not provide an output if the
condition is not satisfied, is executed so that it unconditionally
provides an output to the target. The conditional instruction obtains the
prior value of the target (that is, the value produced by the most recent
instruction preceding the conditional instruction that updated that
target). The condition is evaluated. If the condition is satisfied, an
operation is performed and the result of the operation output to the
target. If the condition is not satisfied, the prior value is output to
the target. Subsequent instructions may rely on the target as an operand
source (whether written to a register or forwarded to the instruction),
prior to the condition evaluation.