Asymmetric hardware support for a special class of threads is provided. Preferably, the special class threads are high-priority, I/O bound threads. In a first aspect, a multithreaded processor contains N sets of registers for supporting concurrent execution of N threads. At least one of the register sets is dedicated for use by a special class of threads, and can not be used by other threads even if idle. In a second aspect, the special class of threads can fill only the a limited portion of the cache memory, in order to reduce flushing of the cache which might otherwise occur.