Systems and methods for executing program instructions in a data processor at a variable rate. In one embodiment, a processor is configured to examine received instructions, identify an execution time associated with each instruction, and generate clock pulses at necessary intervals to obtain the appropriate execution time for each instruction. Instructions may be associated with types or "bins" that are in turn associated with corresponding execution times. The clock pulses may be generated by routing successive pulses through circuits that delay the pulses by desired amounts of time. The processor may also be configured to identify instructions which are input/output (I/O) instructions and are initiated or terminated by completion of handshake procedures and therefore have execution times that vary from one instance to the next.

 
Web www.patentalert.com

< General input/output architecture, protocol and related methods to implement flow control

> Microcontroller unit (MCU) with suspend mode

> Method for recognizing and verifying FIFO structures in integrated circuit designs

~ 00520