An improved method, system, computer program product, and electronic design structures which provides the flexibility to IC designers to be able to relax the design rules to increase the yield and improve the layout productivity is disclosed. In some disclosed approaches, automated interactive aids and batch tools are provided which can assist in optimizing the final layouts for yield at the initial placement and/or routing stages for optimizing yield. Provided in some disclosed approaches are automated capability to layout designers at the mos devices level to configure mos devices as per different DFY recommendations from the foundry without negative effects on the overall chip area (or cell size). The design rules may be relaxed selectively on an instance basis and wherever possible or desirable.