A memory package having a plurality of vertically stacked ball grid arrays. Each of the vertically stacked ball grid arrays has a memory chip coupled thereto. Further, each of the plurality of ball grid arrays includes non-metal mateable alignment features. Each of the plurality of ball grid arrays is coupled to another of the plurality of ball grid arrays to from the vertically stacked memory package.

 
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> Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG

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