A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

 
Web www.patentalert.com

< Catalyst recovery from light olefin FCC effluent

< Process for protecting fiber-reinforced carbon-containing composites against oxidation

> Method of reducing particulates and enhancing burning rate within a combustion chamber

> Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer

~ 00246