An address generating circuit, in which address generation by a modulo addition
is executed at high speed, is provided. The address generating circuit makes, a
two input adder that adds an address and a renewing step, a three input adder and
subtracter that adds the address and the renewing step and further adds the size
of a modulo area to this added result or subtracts the size of the modulo area
from this added result, and a selection judging circuit that generates a selection
signal for selecting one of the outputs from the two input adder and the three
input adder and subtracter, work in parallel and independently. And a multiplexer
selects one of the outputted results from the two input adder and the three input
adder and subtracter based on the selection signal from the selection judging circuit.
