A signal processing circuit having a data input-output (I/O) circuit, a microprocessor,
a dedicated processing circuit, a local memory, and a memory access control circuit
interconnected over a bus. The system bus connects to the data I/O circuit, microprocessor,
dedicated processing circuit, and memory access control circuit. A local memory
bus connects to the local memory. First, second, and third connection circuits
connect between the system bus and local memory bus, between a first local bus
in the dedicated processing circuit and the local memory bus, and between a second
local bus in the data I/O circuit and the local memory bus. The memory access control
circuit controls the first, second, and third connection circuits according to
priorities assigned for the connection circuits and determines which of the second
local bus, first local bus, and system bus will be connected to the local memory bus.
