A semiconductor device including memory cells isolated by a trench that may
be self aligned with a stacked film pattern (7) has been disclosed. The
memory cells may be flash memory cells having an active gate film (2) that
may be thinner than a gate oxide film (30). The active gate film (2) may
be located in a central portion under of a gate electrode (3). The gate
oxide film (30) may be located under end portions of the gate electrode
(3). In this way, a distance between a shoulder portion of a trench (11)
and a gate electrode (3) may be increased. Thus, an electric field
concentration in the shoulder portion of the trench (11) may be decreased
and memory cell characteristics may be improved.
