Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions
   
   

An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.

Прибор и метод для эффективно производить арифметические флаги в системе компьютера. Система вклюает eflags регистрирует к, котор хранят частично вычисленным флагам вычисленным арифметическим блоком логики. , котор хранят частично флаги вычислены в одном цикле. , котор хранят флаги расшифрованы одной из 2 уничтожая инструкций, PRODF или TBIT, в втором цикле.
 
Web www.patentalert.com

< Multiprocessor environment supporting variable-sized coherency transactions

< Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system

> Preserving the content of a first register without affecting the content of a second register

> Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory
~ 00138