A split-gate flash memory structure. The flash memory at least includes a
substrate having a trench therein, a floating gate, a select gate and a
source/drain region. The floating gate is formed inside the trench such
that the upper surface of the floating gate is below the substrate
surface. The select gate is also formed inside the trench above the
floating gate such that the select gate protrudes beyond the substrate
surface. The source/drain region is formed in the substrate on each side
of the select gate. The source/drain region and the floating gate are
separated from each other by a distance. A tunnel oxide layer separates
the floating gate from the substrate and a gate dielectric layer separates
the floating gate from the select gate. A dielectric layer separates the
select gate from the substrate.
