The most significant N bits of each number in a pseudo random sequence are
generated by unidirectionally shifting the previous bits from a first
memory cell toward the Nth memory cell of a sequential register and
generating a new bit in the first memory cell in response to a
predetermined combination of the previous N bits through feedback logic,
for example by NORing the previous N most significant bits, such that
always at least one of the N bits is a zero. N most significant bits are
matched with a least significant bits portion that cycles exactly once for
each most significant bit value. This results in a pseudo random sequence
excluding an upper fraction of one-fourth, one-eighth, . . . ,
(one-half).sup.N of an otherwise power of two range. Embodiments include
right or left shifting, generating reversed sequences, or coupled right-
and left-shifting, in hardware or software implementations.
