A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer. In some embodiments a row of wire bond sites on the land side of adjacent bond fingers is exposed by a common opening in the dielectric layer, providing for a finer pitch interconnect and, accordingly, a higher interconnect density between stacked packages. Also a land grid array package having such a single metal layer tape substrate. Also, a multi-package module including such a single metal layer tape substrate land grid array package stacked over a ball grid array package. Methods for making the substrate are also disclosed.

 
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> Stacked packages and microelectronic assemblies incorporating the same

> Semiconductor device

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