Designing method of an electronic device subjected to a chemical
mechanical polishing process in a fabrication process thereof is
conducted according to the steps of: dividing a substrate surface into
first sub-regions; optimizing a coverage ratio of hard-to-polish regions
in the first sub-regions to fall in a first predetermined range
corresponding to the first sub-regions; dividing the substrate surface
into second sub-regions different from the first sub-regions; and
optimizing a coverage ratio of the hard-to-polish regions in the second
sub-regions to fall in a second predetermined range corresponding to the
second sub-regions, wherein patterns having a shorter edge of 5 .mu.m or
less are excluded from the optimization.