A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern perpendicular to the lower-layer wiring pattern on an imaginary upper-layer wiring layer implemented in the graphics image space, providing a detour pattern including a first detour pattern connected to the upper-layer wiring pattern, providing a plurality of via patterns connecting the lower-layer and upper-layer wiring patterns, and forming a via cell pattern.