A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.