Duplicate data are stored in separate storage units SU(0) 16 and the SU(1) 26, respectively. The storage area in each of the SU(0) 16 and the SU(1) 26 is divided into master storage regions and sub storage regions each of which is allocated alternately to the storage units SU(0) 16 and SU(1) 26 in increments of fixed addresses. The store request is issued to both of the storage units SU(0) 16 and SU(1) 26 allocated the master storage region and the sub storage region, and the fetch request is issued to one of the storage units SU(0) 16 and SU(1) 26 allocated the master storage region from the RSC(0) 34 and RSC(1) 44.

 
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> Power supply control circuit for memories, method thereof and apparatus equipped with memories

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