Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

 
Web www.patentalert.com

< Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions

< Memory subsystem voltage control and method

> Data management architecture

> Offsite management using disk based tape library and vault system

~ 00297