Semiconductor memory device for storing multivalued data

   
   

In the operation of writing the second page, the control circuit precharges the bit line in verifying data "2" in the memory cell when the DDC has data "1" in it after the data cache is set and does not precharge the bit line when the DDC has data "0" in it. As a result, when data "2" has been written into the memory cell, the bit line is at the intermediate potential, which raises the threshold voltage of the memory cell a little.

 
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