Line rate buffer using single ported memories for variable length packets

   
   

A network interface card is provided. The network interface card includes a plurality of pipelined processors. Each of the pipelined processors includes an input socket having at least three single ported memory regions configured to store variable-size data packets. The at least three single ported memory regions enable a downstream processor reading the variable-size data packets from the single ported memory regions to maintain a data throughput to support an incoming line rate of a data stream. The line rate data throughput is maintained after a maximum size data packet has been read by the downstream processor. Methods of method for optimizing throughput between a producing processor and a consuming processor and a processor are also provided.

 
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