A test cell (12) provides boundary scan testing in an integrated circuit
(10). The test cell (12) comprises two memories, a flip-flop (24)
and a latch (26), for storing test data. A first multiplexer (22)
selectively connects one of a plurality of inputs to the flip-flop (24).
The input of the latch (26) is connected to output of the flip-flop (24).
The output of the latch (26) is connected to one input of a multiplexer
(28), the second input to the multiplexer (28) being a data input
(DIN) signal. A control bus (17) is provided for controlling the multiplexers
(22, 28), flip-flop (24) and latch (26). The test cell allows
input data to be observed and output data to be controlled simultaneously.
