A semiconductor memory device comprising: a source diffusion layer formed on a
semiconductor substrate and connected to a fixed potential line; a plurality of
columnar semiconductor layers arranged in a matrix form and formed on the source
diffusion layer and each having one end connected to the source diffusion layer
commonly, the columnar semiconductor layer taking a first data state with a first
threshold voltage that excessive majority carriers are accumulated in the columnar
semiconductor layer, and a second data state with a second threshold voltage that
excessive majority carriers are discharged from the columnar semiconductor layer;
a plurality of drain diffusion layers each formed at the other end of the columnar
semiconductor layer; a plurality of gate electrodes each opposed to the columnar
semiconductor layer via a gate insulating film, and connected to the word line;
a plurality of word lines each connected to corresponding the gate electrodes;
and a plurality of bit lines each connected to corresponding the drain diffusion
layers, the bit lines being perpendicular to the word lines.
