A method and structure for a CMOS device comprises depositing a silicon over
insulator
(SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined
thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench
isolation (STI) region over the BOX substrate, wherein the STI region is configured
to have a generally rounded corner; forming a gate structure over the gate dielectric;
depositing an implant layer over the SOI wafer; performing one of N-type and P-type
dopant implantations in the SOI wafer and the implant layer; and hearing the device
to form source and drain regions from the implant layer and the SOI wafer, wherein
the source and drain regions have a thickness greater than the predetermined thickness
of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
