Testing register bits and in particular bitmask registers is a method
employed in many computer architectures (e.g., IBM PowerPC, IA32, VAX,
etc.) to manage instruction flow within a processor. Since the testing or
scanning of bitmask registers for the first occurrence of a logic state
(e.g., logic one) is done quite often, register scanning is implemented in
hardware in these processors. Other computer architectures (e.g., Intel
IA64) manage instruction flow with alternate methods and therefore do
register scanning as a software construct. When software written for the
first computer architecture (e.g., IBM PowerPC) is ported to a system with
IA64 architecture, the program would execute with reduced speed. The IA64
architecture uses the EPIC instruction protocol and as such executes
predicate instructions that employ a predicate register where each bit of
the predicate register can be associated as the true or false result of a
comparison. To scan a register in the IA64 architecture the register
contents are loaded into the predicate register and a sequence of
predicate instructions are executed in the order that the bits are to be
scanned for the desired condition. The sequence of predicate instruction
sequence returns the register bit that passes the predicate condition. In
this manner the speed of register scanning necessary for the ported
software can be increased over the software scanning of the IA64
architecture.