An interface between memories having different write times is described.
The interface includes a latch for capturing address and data information
during a memory access by a processor of a first memory device. The
interface also includes an index counter for providing frame management.
The interface also includes a variable identity array logic for
determining what data is to be written into a second memory device and
address generation logic to determine where the data is to be stored in
the second memory device. Additionally, the interface includes data
validity logic to ensure that the data being written into the second
memory device is valid. As a result, the processor can operate in
substantially real time and can restore itself after detecting an event
upset using the data stored in the second memory device.