Provided is a wafer level chip scale package that reduces the parasitic
capacitance generated between ball pads and the solder balls, and
enhances the joint reliability between the ball pads and the solder
balls. The wafer level chip scale package provides a conductive pattern
in each ball pad section, on which a solder ball is mounted, so as to
have a spiral or mesh shape, provides a space defined by the conductive
pattern such that a first dielectric layer under the conductive pattern
is exposed, and provides the solder ball on a top surface of each ball
pad section such that part of the solder ball is inserted into the space
defined by the conductive pattern. When viewed from the top, the
dielectric layer is exposed from each ball pad section by an area of
about 50% or less.