The present invention discloses a shift register circuit comprising a plurality of shift register units and a bus, wherein the bus couples to each shift register unit. Each shift register unit comprises a shift register, a first selector circuit, and a second selector circuit. The shift register has an input and an output. The first selector circuit is coupled to the input, while the second selector circuit is coupled to the output. The first selector circuit and the second selector circuit selectively couple to the bus or the next shift register unit.