A semiconductor integrated circuit includes a memory, a BIST main circuit
and a BIST sub circuit. The BIST sub circuit is to generate a row address
pattern or a column address pattern of the memory and includes a boundary
address generation circuit for alternately generating a top address and a
bottom address of the memory for at least one of the row address pattern
and the column address pattern. The BIST main circuit is provided in
common with a plurality of memories and the BIST sub circuit is
individually provided corresponding to the memories. The boundary address
generation circuit includes a top address memory unit for storing the top
address and a top/bottom address generation unit for reading out the top
address and alternately outputting the top address and the bottom
address.