Multichip graphics processing subsystems include at least three distinct
graphics devices (e.g., expansion cards) coupled to a high-speed bus
(e.g., a PCI Express bus) and operable in a distributed rendering mode.
One of the graphics devices provides pixel data to a display device, and
at least one of the other graphics devices transfers the pixel data it
generates to another of the devices via the bus to be displayed. Where
the high-speed bus provides data transfer lanes, allocation of lanes
among the graphics devices can be optimized.