A Hardware Description Language (HDL) utilizing a Term Rewriting System
(TRS) is provided that simplifies handling of clocks, and signaling
between various clock domains of a multi-clock domain circuit
specification. A specific clock data type is supplied for use with clock
signals. Using the clock data type, and other requirements of a circuit
specification, clock domain crossing between domains of clocks of the
same clock family is handled implicitly. For clock domain crossing
between clock domains driven by clocks of different clock families, a
"hardware approach" and a "linguistic approach" are provided. A "hardware
approach" provides facilities to explicitly specify a synchronizer,
using, in part, TRS rules. A "linguistic approach" allows a designer to
abstracts the instantiation of synchronizers and instead specify a
circuit specification in terms of differently clocked interfaces.