An ECC circuit (103) is located between I/O terminals (104.sub.0-104.sub.7) and page buffers (102.sub.0-102.sub.7). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (101.sub.0-101.sub.7), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (101.sub.0-101.sub.7). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528.times.8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).