Methods and apparatus are provided for allowing simultaneous memory accesses. A generator tool analyzes logic to determine the number of simultaneous memory accesses to the same data structure. Memory is divided into blocks having sequential addresses based on the number of simultaneous memory access specified, e.g. base addresses at A, A+B, A+2B, A+3B. Individual slave side arbiters are assigned to each block of memory. Addresses for memory accesses associated with master components or master ports are modified to allow simultaneous access to multiple memory locations.