A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device based on priorities assigned to the master device or provides information about following requests. The refresh control unit determines a refresh timing of the dynamic memory based on the existence of the following requests and an idle state of banks constituting the dynamic memory. Accordingly, the dynamic memory refresh controller may maximize a refresh trigger interval by changing the management order of the requests from the master device based on the priority of the response latency.