The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for providing a delayed signal of the test signal, and circuitry for comparing the logical state of the test signal and the delayed signal and issuing an attack indication whenever the signals are different.

 
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< On-chip multi-core type tamper resistant microprocessor

> System, method and storage medium for bus calibration in a memory subsystem

> Security for external system management

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