Disclosed is a phase change memory device including: a semiconductor substrate formed with a first insulating interlayer having a first contact hole; a contact plug formed in such a manner so as to be recessed within the first contact hole; a catalyst layer formed on the contact plug in such a manner so as to fill the first contact hole; a second insulating interlayer formed on the first insulating interlayer including the catalyst layer having a second contact hole through which the catalyst layer is exposed; a carbon nano tube lower electrode formed within the second contact hole in such a manner so as to come in contact with the catalyst layer; a phase change layer formed on the carbon nano tube lower electrode and a second insulating interlayer portion around the second contact hole; and an upper electrode formed on the phase change layer.