A Parallel Test Architecture (PTA) is provided that facilitates concurrent
test, debug or programmable configuration of multiple electronic circuits
(i.e., simultaneously). The PTA includes a communications path, a primary
test controller, and a number of local test controllers. The primary
controller provides stimulus, expected, and mask data to the local
controllers over the communications path. The local controllers apply the
stimulus data to the electronic circuits, receive resultant data
generated by the circuits in response to the stimulus data, and locally
verify the resultant data against the expected data substantially
concurrently. When the communications path is implemented as an IEEE
1149.1 (JTAG) test bus, the primary controller can provide the expected
and mask data to the local controllers over the TDO and TRSTN lines while
the TAP controllers of the electronic circuits are in the Shift-IR or
Shift-DR state to enable concurrent testing over a traditional five wire
multi-drop IEEE 1149.1 test bus.