A bit line precharge circuit, a method of precharging a bit line and an
SRAM device incorporating the circuit or the method. In one embodiment,
the bit line precharge circuit includes: (1) a word line driver coupled
to word lines of the SRAM array and configured to operate at a word line
driver voltage and (2) a bit line precharge circuit coupled to bit lines
of the SRAM array and configured to precharge the bit lines to a
precharge voltage substantially lower than the word line driver voltage.