A code is provided which outputs a predetermined code enable signal by
executing a simple control, depending on a clock signal frequency, with
an optimal circuit scale. A multiplexer receives integers which are
relatively prime, and outputs either of them to an adder, depending on
comparator output signal. The adder adds an integer latched by the
register and an integer output by the multiplexer, and outputs the result
via a multiplexer to the register. The register latches and outputs the
received integer to the comparator with a sampling clock signal
frequency. In accordance with a threshold set based on the integers and
the number of bits of the adder or the register, the comparator outputs a
signal having the High state only when the output integer of the register
satisfies the threshold condition. The code outputs this as a code enable
signal.