A memory device including an array of memory cells, and a register circuit
to store a value representative of a period of time to elapse before the
memory device is ready to receive a command when recovering from a power
down mode is provided in an embodiment. The command specifies an access
to the array of memory cells. A delay lock loop circuit synchronizes data
transfers using an external clock signal. The delay lock loop circuit
reacquires synchronization with the external clock signal during the
period of time.