Non-volatile memory devices include a tunnel insulating layer on a channel
region of a substrate, a charge-trapping layer pattern on the tunnel
insulating layer and a first blocking layer pattern on the
charge-trapping layer pattern. Second blocking layer patterns are on the
tunnel insulating layer proximate sidewalls of the charge-trapping layer
pattern. The second blocking layer patterns are configured to limit
lateral diffusion of electrons trapped in the charge-trapping layer
pattern. A gate electrode is on the first blocking layer pattern. The
second blocking layer patterns may prevent lateral diffusion of the
electrons trapped in the charge-trapping layer pattern.