A package design method for a semiconductor device of designing a package
including a package substrate provided with a wiring pattern, a chip
mounted on the package substrate, and a sealing resin which covers the
package substrate and the chip, and the wiring pattern including an
external connection terminal and an internal connection terminal
connected to the chip, the method comprising: setting an acceptable noise
value of the package; designing a package layout on the basis of
information on connection between the package substrate and the chip; and
performing an optimization on package layout data so that an amount of
noises remains within a range which is set beforehand, on the basis of
the package layout data obtained in the designing process of the package
layout.