A read command AL shifting unit shifts a read command for a predetermined additive latency, to output a shifted read command. A write command AL shifting unit shifts a write command for the predetermined additive latency to output a first shifted write command. A write command CL shifting unit shifts the first shifted write command for a predetermined cas latency to output a second shifted write command. A write address controller generates an address control signal in response to the shifted read command and the first shifted write command. An address transfer circuit transfers an address in response to the address control signal. Other embodiments are also described.