A memory architecture and circuits for minimizing current leakage in the
memory array. Subdivisions of the memory array each have local power
grids that can be selectively connected to power supplies, such that only
an accessed subdivision will receive power to execute the memory access
operation. The memory array can further include databuses which are
precharged to one voltage during idle times and a second voltage during
active read cycles, which reduces leakage current in datapath circuitry
connected to the databuses within the memory array blocks.